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HD155101BF
RF Single-chip Linear IC for GSM and EGSM Systems
ADE-207-256A (Z) 2nd Edition September 1998 Description
The HD155101BF was developed for GSM and EGSM cellular systems, and integrates most of the functions of a transceiver. The HD155101BF incorporates the bias circuit for a RF LNA, a 1st mixer, 1stIF amplifier, 2nd mixer, AGC amplifier and an IQ quadrature demodulator for the receiver, and an IQ quadrature modulator and offset PLL for the transmitter. Also, on chip are the dividers for the 1st & 2nd local oscillator signals and 90 phase splitter. Moreover the HD155101BF includes control circuits to implement power saving modes. These functions can operate down to 2.7 V and are housed in a 48-pin LQFP SMD package. Hence the HD155101BF can form a small size transceiver handset for GSM and EGSM by adding a PLL frequency synthesizer IC, a power amplifier and some external components. See page 7 "Configuration". The HD155101BF is fabricated using a 0.6 m double-polysilicon Bi-CMOS process.
Functions
Receiver (RX) * * * * * * Low Noise Amplifier (LNA) bias circuit 1st mixer IF amplifier 2nd mixer Automatic gain control amplifier (AGC) IQ demodulator with 90 phase splitter
Transmitter (TX) * IQ modulator with 90 phase splitter * Offset PLL Down converter Phase comparator TX VCO driver
HD155101BF
Others * IF dividers * Power saving circuit * IFVCO
Features
* Highly integrated RF processing for hand-portables * Wide operating frequency RX: RF: 925 to 960 MHz 1st IF: 130 to 300 MHz 2nd IF: 26 to 60 MHz TX: RF: 880 to 915 MHz IF: 156 to 360 MHz * Offset PLL architecture reduces TX spurious * Low current consumption (Vcc = 3 V) RX mode: 42.5 mA Typ (including IFVCO current (2.5 mA Typ)) + LNA transistor current (5.6 mA Typ) TX mode: 38.0 mA Typ (including IFVCO current (2.5 mA Typ)) Idle mode: 1 A Typ * Operating supply voltage: Phase comparator and TX VCO driver circuits: 2.7 to 5.25 V Other blocks: 2.7 to 3.6 V * Operating temperature range: -20 to +85C * 48 pin SMD Low Profile Quad Flat Package (LQFP): FP-48
HD155101BF
Pin Arrangement
The HD155101BF is housed in a 48-pin LQFP SMD package to which is suitable for applications where space is limited. "Pin Functions" shows the arrangement and roles assigned for each pin of the HD155101BF.
MIX1OUTB
GNDMIX1
MIX1OUT
VCCMIX1
MIX1INB
RFLOIN
MIX1IN
48 POONRX1 POONRX2 RFOUT VCCLNA GNDLNA RFIN POONTX VCCPLL GNDPLL VCOIN VCCCOMP PLLOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 ICURAD
47
46
45
44
43
42
41
40
39
38
37 36 35 34 33 32 31 30 29 28 27 26 25 24 IFVCOI MIX2OB GNDAGC VCCAGC AGCOUT AGCOUTB VCCDIV GNDDIV VCONT IOUT IOUTB QOUT QOUTB
14 QINB
15 QIN
16 IINB
17 IIN
18 MODB
19 MOD
20 VCCIQ
21 IFLO
22 GNDIQ
23 IFVCOO
(Top View)
MIX2O
GNDIF
VCCIF
IFINB
IFIN
HD155101BF
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol POONRX1 POONRX2 RFOUT VCCLNA GNDLNA RFIN POONTX VCCPLL GNDPLL VCOIN VCCCOMP PLLOUT ICURAD Input/ Output Input Input Output Vcc Gnd Input Input Vcc Gnd Input Vcc Output Input Meaning of symbol POwer ON for RX1 POwer ON for RX2 RF signal OUTput VCC of LNA block GND of LNA block RF signal INput POwer ON for TX VCC of O PLL block GND of O PLL block VCO signal INput VCC of phase COMParator OPLL OUTput I CURrent AD just Function If `H', LNA and MIX1 are active. Other receiver blocks don't care. LNA and MIX1 don't care. If `H', Other receiver blocks are active. Open collector type output of LNA. The collector of LNA transistor. Power supply of LNA Ground of LNA Input of LNA. The base of LNA transistor If `H', the blocks for transmitter are active. The reciver blocks don't care. Power supply for offset PLL except phase comparator Ground of offset PLL Input of Tx. VCO signal Power supply for just phase comparator of offset PLL Current output to control and modulate Tx. VCO This pin should be connected external loop filter. This pin should be connected an external R to determine charge pump current of phase comparator Q negative signal input of IQ quadrature modulator Q positive signal input of IQ quadrature modulator I negative signal input of IQ quadrature modulator I positive signal input of IQ quadrature modulator Negative output of IQ quadrature modulator Positive output of IQ quadrature modulator Power supply of IQ block IF local signal input to be fed to divider Ground of IQ block Emitter of IFVCO transistor Base of IFVCO transistor
14 15 16 17 18 19 20 21 22 23 24
QINB QIN IINB IIN MODB MOD VCCIQ IFLO GNDIQ IFVCOO IFVCOI
Input Input Input Input Output Output Vcc Input/ Output Gnd Output Input
Q signal INput Bar Q signal INput I signal INput Bar I signal INput MODulator output Bar MODulator output VCC of IQ block IF LOcal signal input/output GND of IQ block IFVCO Output IFVCO I nput
HD155101BF
Pin Function (cont)
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol QOUTB QOUT IOUTB IOUT VCONT GNDDIV VCCDIV AGCOUTB AGCOUT VCCAGC GNDAGC MIX2OB MIX2O IFINB IFIN GNDIF VCCIF MIX1OUT MIX1OUTB RFLOIN VCCMIX1 GNDMIX1 MIX1INB MIX1IN Input/ Output Output Output Output Output Input Gnd Vcc Output Output Vcc Gnd Output Output Input Input Gnd Vcc Output Output Input Vcc Gnd Input Input Meaning of symbol Q signal OUTput Bar Q signal OUTput I signal OUTput Bar I signal OUTput Voltage of AGC CONTrol GND of DIVider block VCC of DIVider block AGC OUTput Bar AGC OUTput VCC of AGC block GND of AGC block MIX2 Output Bar MIX2 Output 1stIF signal INput Bar 1stIF signal INput GND of IFMIX2 block VCC of IFMIX2 block MIX1 Output MIX1 Output Bar RF LOcal signal INput VCC of MIX1 block GND of MIX1 block MIX1 I nput Bar MIX1 I nput Function Q negative signal output of IQ quadrature demodulator Q positive signal output of IQ quadrature demodulator I negative signal output of IQ quadrature demodulator I positive signal output of IQ quadrature demodulator The DC voltage input to control the power gain of AGC Ground of divider to make IF local signals Power supply of divider to make IF local signals AGC negative signal output to be fed to IQ quadrature demodulator AGC positive signal output to be fed to IQ quadrature demodulator Power supply of AGC Ground of AGC 2nd mixer (MIX2) negative signal output to be fed to AGC 2nd mixer (MIX2) positive signal output to be fed to AGC IFAMP negative signal input for 1st IF signal IFAMP positive signal input for 1st IF signal Ground of IFAMP and 2nd mixer (MIX2) Power supply of IFAMP and 2nd mixer (MIX2) 1st mixer (MIX1) positive signal output 1st mixer (MIX1) negative signal output RF 1st local signal input to be fed to 1st mixer (MIX1) and the down converter of offset PLL Power supply of 1st mixer (MIX1) Ground of 1st mixer (MIX1) 1st mixer (MIX1) negative signal input 1st mixer (MIX1) positive signal input
225 MHz
947 MHz
1172 MHz
947 MHz IFIN IFINB 46 36 Vref (Mix1) 35 34 33 *2 Bias generator Vref (AGC) 45 MHz Linearizer 31
Vref (Div, Tx) /2(90 deg)
GNDMIX1
VCCMIX1
RFLOIN
VCCIF
GNDIF
MIX1IN
MIX1INB
MIX1OUTB
Block Diagram
48 MIX2OB GNDAGC VCCAGC AGOUT 45 MHz AGCOUTB 32 VCCDIV GNDDIV 30 29 VCONT IOUT 0 to 100 kHz 28 IOUTB 0 to 100 kHz 27
IFVCO Bias Circuit
HD155101BF
47
45
44
43
MIX1OUT
42
41
40
39
38
MIX2O 37 45 MHz
*1 POONRX1 1 *1 POONRX2 2 Vref Vref (IF) (Mix2) 1172 MHz *2 270 MHz
RFOUT 3
LNA Vref Bias (LNA) Circuit
4 GNDLNA 5 1172 MHz
VCCLNA
7 MHz /2 /2 (90 deg)
Vref (Demod)
RFIN /3 Vref (Div, Rx) /2, /12 /2
6 /2 (90 deg)
*1 POONTX 270 MHz
Vref (PLL)
7
VCCPLL
GNDPLL
x.VCO VCOIN 10 902 MHz 540 MHz
Vref (Mod)
VCCCOMP
11
Phase detector
270 MHz
9
902 MHz
8
QOUT 0 to 100 kHz 26 QOUTB 0 to 100 kHz 25 VCCIQ IFLO GNDIQ IFVCOO IFVCOI
PLLOUT 12 MODB MOD 15 16 17 18 19
ICURAD
13
14
20
21
22
23
24
0 to 100 kHz QIN
0 to 100 kHz QINB
Notes: 1. H = Active, L = Off All biases are H active 2. When POONRX1 = `H' and POONRX2 = `L', bias generator will be off. When Bias generator is off, all circuits will be off.
0 to 100 kHz IINB
0 to 100 kHz IIN
IFLO To Synth.
Vtune
Configuration
225 MHz 925 to 960 MHz LNA
bias circuit
45 MHz LC filter AGC I&Q Demo. 45 MHz 270 MHz I Q
RF SAW filter
IF SAW filter
RF filter
1150 to 1185 MHz TCXO 13 MHz HD155017T LPF Dual PLL1 synth.
RF VCO IFVCO PLL2 540 MHz /2
HD155101BF
90 deg Shift /2 B.B. Block 90 deg Shift /2
/6
270 MHz 270 MHz HPA Module Loop filter buffer 880 to 915 MHz Phase Detector 270 MHz I&Q Mod I Q
HD155101
HD155101BF
225 MHz
947 MHz
947 MHz IFIN IFINB 46 MIX2OB 36 Vref (Mix1) VCCAGC 34 270 MHz AGOUT 45 MHz 33 AGCOUTB 32 Linearizer VCCDIV 31 GNDDIV 30 VCONT 29 IOUT 28 IOUTB 27 540 MHz QOUT 26 QOUTB 25 MOD VCCIQ IFLO GNDIQ IFVCOO IFVCOI 20 21 22 23 24 Vref (AGC) 45 MHz Vref Vref (IF) (Mix2) GNDAGC 35 45 44 43 42 41 40 39 38 37 45 MHz
MIX1IN
MIX1INB
GNDMIX1 VCCMIX1 RFLOIN
VCCIF
GNDIF
1172 MHz MIX1OUTB
48
47
POONRX1 1
A GSM Application Example
POONRX2 2 1172 MHz
RFOUT 3
LNA Vref Bias Circuit (LNA)
MIX1OUT
MIX2O
DAC 10 bit DAC 10 bit ADC 12 bit Base Band Interface Processing DAC 10 bit
VCCLNA 4 *2 Bias generator
GNDLNA 5 1172 MHz
947 MHz /2 /2 (90 deg) Vref Vref (Div, Rx) /2, /12 /3 /2
RFIN
6 Vref (Div, Tx) /2(90 deg) /2 (90 deg)
POONTX 270 MHz
Vref (PLL)
7
Base Band System Controller & Physical Layer Processor ADC 12 bit DAC 10 bit
VCCPLL
GNDPLL Vref (Mod)
(Demod)
PA
ALC
VCOIN 10
Tx.VCO
902 MHz
VCCCOMP 11
Phase detector
270 MHz
9
902 MHz
8
13 MHz
PLLOUT 12 QIN QINB IINB IIN MODB 15 16 17 18 19
ICURAD
13
14
UHF(RF) PLL Synth.
VHF(IF) PLL Synth.
Dual PLL synth.
HD155101BF
Functional Operation
The HD155101BF has been designed from system stand point and incorporated a large number of the circuit blocks necessary in the design of a digital cellular handset. Receiver Operation The HD155101BF incorporates a LNA bias circuit for an external RF transistor, whose NF and power gain can be better selected. This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first mixer section. The RF signal is combined with a high side local oscillator (LO) signal to generate a wanted first IF signal in the 130 to 300 MHz range. The 1st mixer circuit uses a double-balanced Gilbert cell architecture, which has open collector differential outputs. If, at 225 MHz, a 800 LC load is connected to the mixer's outputs then a SSB NF of 9.0 dB with a gain of 7.0 dB is realizable. The corresponding input compression point is -11 dBm, which allows the device to be used within a GSM and EGSM system. A filter is used after the 1st mixer to provide image rejection and the conditioned signal is then passed through an intermediate amplifier, before being down converted to a second IF in the range of 26 to 60 MHz. The second mixer can generate a 45 MHz 2nd IF, if a 270 MHz 2nd LO signal is used. The 2nd LO is obtained by dividing the IFLO signal by 2. The 2nd mixer also uses the Gilbert cell architecture, but with internal resistive differential outputs of 300 . IF amplifier and second mixer has a SSB NF of 5.6 dB, a power gain of 12 dB and an input compression point of -25 dBm. In order to improve the blocking characteristics of the device an external LC resonator across the differential outputs of the second mixer is recommended. The signal is then passed to the AGC circuit, which has a dynamic range of more than 80 dB (-42 dB to +55 dB Typ) and is controlled by a DC voltage, which is generated by the microprocessor. This DC control range is from 0.15 V to 2.3 V. The AGC, which is designed for the GSM system, provides a linearity of 1.0 dB in any 20 dB window. The outputs of the AGC are 2 k differential and are connected the external supply via inductors. The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO signal to the same frequency as the 2nd IF before passing this local signal through a phase splitter / shifter in order to generate the in phase and quadrature IQ components. The phase accuracy of the IQ demodulator is < 1 and the amplitude mismatch is < 0.5 dB. In order to accommodate different baseband interfaces the HD155101BF IQ differential outputs have a voltage swing of 2.4 Vp-p and a DC offset of < 60 mV. Within each output stage a 2nd order Butterworth filter (fc = 210 kHz), is used to improve the blocking performance of the device. In order to allow flexibility in circuit implementation the HD155101BF can configured to use either a single-ended or balanced external circuitry and components.
HD155101BF
Poutput 3 Vcc Pinput 4 RFOUT VCCLNA LNA Vref
LNA bias GNDLNA circuit 5 6 RFIN
Figure 1 LNA Bias Circuit Transmitter Operation The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a power amplifier. The common mode DC voltage range of the modulator inputs is 0.8 to 1.2 V and they have 2.4 Vp-p Max differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The LO signals are generated by dividing the IFLO signal by 2 and then passing them through a phase splitter / shifter. The IF signals generated are then summed and produce a single modulated IF signal which is amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31 dBc. However, if the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression can be improved better than 40 dBc easily. In addition, upper side-band suppression is better than 35 dBc. Within the offset PLL block there is a down converter, a phase comparator and a VCO driver. The down converter mixes the 1st LO signal and the TX VCO to create a reference LO signal for use in the offset PLL circuit. The phase comparator and the VCO driver generate an error current, which is proportional to the phase difference between the reference IF and the modulated IF signals. This current is used in a 2nd order loop filter to generate a voltage, which in turn modulates the TX VCO. In order to optimize the PLL loop gain, the error current value can be modified by changing the value of an external resistor - ICURAD. In order to accommodate a range of TX VCO, the offset PLL circuit has been designed to operate with a supply voltage of up to 5.25 V. Operating Modes The HD155101BF has the necessary control circuitry to implement the necessary states within the GSM system. Also provided is a power save mode which reduces the current consumption of the device by powering down unnecessary function blocks. Three pins are assigned for mode control, POONRX1, POONRX2 and POONTX. Table 1 shows the relationship between the pins and the required operating mode. Control of these pins are by the system controller. As per GSM requirements the TX and RX sections are not on at the same time. For the receiver there is a calibration mode for which the LNA bias circuit and 1st mixer are switched off. During this period the gain of the AGC can be adjusted. Also the DC offsets of the IQ demodulator are measured and subsequently canceled. In order to change between the RX and TX modes a state called "warm-up" is used to ensure that the LO
HD155101BF
Power saving is implemented through use of the idle mode. All function blocks of the HD155101BF are switched off until such time as the system controller commends the device to power up again. Table 1 Operating Modes with Power Saving
Receive (Rx) Mode switch POONRX1 (pin 1) POONRX2 (pin 2) POONTX (pin 7) HD155101BF circuit status LNA bias 1st mixer IF AMP 2nd mixer AGC IO demodulator Divider (Rx.) Divider (Tx.) IO modulator Offset PLL RF 1st local buffer IF local buffer IFVCO Total current H H L ON ON ON ON ON ON ON OFF OFF OFF ON ON ON 42.5 mA Typ Calibrate (Cal) L H L OFF OFF ON ON ON ON ON OFF OFF OFF ON ON ON 32 mA Typ Warm-up (Lo-ON) L L L OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON 10.5 mA Typ Transmit (Tx) L L H OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON 38 mA Typ Idle (PS) H L Don't care OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF 1 A Typ
4.615ms The slots of GSM system Operating modes of the HD155101BF POONRX1(pin 1) POONRX2(pin 2) POONTX (pin 7) Power Amplifier ON UHF PLL synth. ON UHF PLL synth. load VCO control voltage of UHF PLL synth. 7 0 Rx Cal 1 2 3 Tx Cal Rx Lo-ON Tx ON
Lo-
4.615ms 5 6 7 0 Rx Cal Rx ON
Lo-
4
1
2
3 Tx
4
5
6
7
0
1
Mon
Mon Cal
Lo-
Rx Lo-ON Tx ON
Rx ON
Lo-
PS
Idle(PS) mode don't care
HD155101BF
IFVCO Operation The HD155101BF incorporates an IFVCO circuit. The IFVCO circuit consists of an IFVCO transistor and a bias circuit for it, whose current are 2.0 mA and 0.5 mA respectively. If an internal IFVCO is used, treat pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) as shown figure 3-(a). Using an external IFVCO, pin 23 (IFVCOO) and pin 24 (IFVCOI) cannot be connected any pattern and component, and any component to feed direct current must be also removed from pin 21 (IFLO). If pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) are treated as shown figure 3-(b), current consumption will decrease 2.0 mA.
IFVCO bias circuit IFVCOO IFVCOI IFVCOO IFLO IFLO 21 23 24 HD155101BF 21 23 24
IFVCO bias circuit HD155101BF IFVCOI Vtune PLL IFLO synth.
Vtune Vcc PLL IFLO synth. (a) using an internal IFVCO
External IFVCO
(b) using an external IFVCO
Figure 3 Control Diagram for Operating Mode Selection
HD155101BF
Absolute Maximum Ratings
Any stresses in excess of the absolute maximum ratings can cause permanent damage to the HD155101BF.
Item Power supply voltage (VCC) Power supply voltage (VCCCOMP) Pin voltage Maximum power dissipation Operating temperature Storage temperature Symbol VCC VCCCOMP VT PT Topr Tstg Rating -0.3 to +4.0 VCC to +5.5 -0.3 to VCC + 0.3 (6.0 Max) 400 -20 to +85 -55 to +125 Unit V V V mW C C
HD155101BF
Electrical Characteristics (Ta = 25C)
Specifications
Applicable pins 4, 8, 20, 31, 34, 41, 45 11 VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V VCCCOMP = 3.0V VCC = 3.0V 1 2 7 1 2 7 25, 26 27, 28 25, 26 27, 28 25, 26 27, 28 14, 15 16, 17 14, 15 16, 17 4, 8, 20, 31, 34, 41, 45, 11 4, 8, 20, 31, 34, 41, 45, 11 4, 8, 20, 31, 34, 41, 45, 11 4, 8, 20, 31, 34, 41, 45, 11 from PS mode from PS mode
Item Power supply voltage (1) Power supply voltage (2) Power supply current (Rx.) Power supply current (Tx.) Power supply current (Lo-ON) Power saving mode supply current Power up time (Rx.) Power up time (Tx.) Power on control voltage range (Rx1, Rx2, Tx) Power off control voltage range (RX1, Rx2, Tx) I/Q common-mode output voltage I/Q differential output swing
Symbol VCC VCCCOMP ICC(Rx.) ICC(Tx.) ICC(Lo-ON) ICC(PS) t up(Rx.) t up(Tx.) VthonRX1 VthonRX2 VthonTX VthoffRX1 VthoffRX2 VthoffTX VIOcom/ VQOcom VIOsw/ VQOsw VIOoffset/ VQOoffset VIIcom/ VQIcom VIIsw/ VQIsw
Min 2.7 2.7 -- -- -- -- -- -- 2.3
Typ 3.0 3.0 42.5 38.0 10.5 1.0 1.5 0.2 --
Max 3.6 5.25 60.0 55.0 15.0 10.0 (5.0) (0.5) --
Unit V V mA mA mA A sec sec V
Test Conditions
Note
--
--
0.8
V
VCC = 3.0V
1.1 2.4
1.3 3.0
1.5 --
V Vp-p
VCC = 3.0V VCC = 3.0V VIOUT - VIOUTB VQOUT - VQOUTB VCC = 3.0V VIOUTDC - VIOUTBDC VQOUTDC - VQOUTBDC VCC = 3.0V VCC = 3.0V VIIN - VIINB VQIN - VQINB
I/Q output offset voltage
-60
0
+60
mV
I/Q common-mode input voltage I/Q differential input swing
(0.8) --
1.0 2.0
(1.2) (2.4)
V Vp-p
Note: ( ) : These data are actual spread, not guaranteed.
HD155101BF
Block Specifications * Specifications of LNA
Item Frequency (RF) Power gain Noise figure i/p IP3 o/p IP3 i/p CP o/p CP Load Z i/p Z i/p VSWR o/p VSWR I CC @LNA Trs. Min 925 -- -- -- -- -- -- -- -- -- -- 4.7 Typ 940 18.0 1.75 -1.0 16 -11.5 5.5 50 50 1.5 1.5 5.6 Max 960 -- -- -- -- -- -- -- -- -- -- 6.8 mA Unit MHz dB dB dBm dBm dBm dBm RF = 940MHz , Pin = -50dBm RF = 940MHz RF1 = 940.8MHz, RF2 = 941.6MHz RF1 = 940.8MHz, RF2 = 941.6MHz RF = 940MHz RF = 940MHz 50 Typ 50 Typ RF = 940MHz, 50 RF = 940MHz, 50 Only Trs. current Test Conditions
Note: These AC characteristics are shown for reference only and do not form part of the HD155101BF component specification.
* Specifications of Mixer 1 (Output Load = 400 + 400 balanced)
Item Frequency (RF) Frequency (LO) Frequency (IF) Conversion gain Noise figure i/p IP3 o/p IP3 i/p CP o/p CP RF i/p VSWR LO i/p VSWR IF o/p VSWR Min 925 1055 (130) 4.5 (6.0) -- -- -13.5 (-9.5) -- -- -- Typ 940 1165 225 7.0 9.0 -1.0 6.0 -11.0 -5.0 1.5 1.5 1.5 Max 960 1260 (300) 9.0 (12.0) -- -- (-8.0) (-0.5) (2.0) (2.0) (2.0) Unit MHz MHz MHz dB dB dBm dBm dBm dBm RF = 940MHz/Pin = -50dBm, LO = 1165MHz/Pin = -10dBm, IF = 225MHz RF = 940MHz, LO = 1165MHz/Pin = -10dBm, IF = 225MHz RF1 = 940.8MHz, RF2 = 941.6MHz, LO = 1165MHz/Pin = -10dBm RF1 = 940.8MHz, RF2 = 941.6MHz, LO = 1165MHz/Pin = -10dBm RF = 940MHz, LO = 1165MHz/Pin = -10dBm, IF = 225MHz RF = 940MHz, LO = 1165MHz/Pin = -10dBm, IF = 225MHz RF = 940MHz, 50 RF = 1165MHz, 50 RF = 225MHz, 800 (400 + 400 Balanced) Test Conditions
HD155101BF
* Specifications of IFAmp + Mixer 2
Item Input frequency (IF1) Frequency (LO2) Output frequency (IF2) Conversion gain Noise figure i/p IP3 o/p IP3 i/p CP o/p CP Isolation Min (130) (156) (26) 9.0 (4.5) -- -- -27.5 (-18.0) (55) Typ 225 270 45 12.0 5.6 -16.0 -4.0 -25.0 -14.0 60 Max (300) (360) (60) 14.5 (7.0) -- -- (-23.0) (-11.0) -- Unit MHz MHz MHz dB dB dBm dBm dBm dBm dB IF1 = 225MHz/Pin = -40dBm, IFLO = 540MHz/Pin = -10dBm, IF2 = 45MHz IF1 = 225MHz, IFLO = 540MHz/Pin = -10dBm, IF2 = 45MHz IF11 = 225.8MHz, IF2 = 226.6MHz, IFLO = 540MHz/Pin = -10dBm IF11 = 225.8MHz, IF2 = 226.6MHz, IFLO = 540MHz/Pin = -10dBm IF1 = 225MHz, IFLO = 540MHz/Pin = -10dBm, IF2 = 45MHz IF1 = 225MHz, IFLO = 540MHz/Pin = -10dBm, IF2 = 45MHz Between mixer 1 outputs and IFAmp inputs LO2 = IFLO/2 Test Conditions
Note: ( ) : These data are actual spread, not guaranteed.
* Specifications of AGC
Item Input frequency Control voltage range Gain range Gain linearity Gain 1 Gain 2 Gain 3 i/p CP 1 i/p CP 2 i/p CP 3 Min (26) 0.15 89 (-1.0) 45 13 -55 (-64) (-34) (-22) Typ 45 -- 98 -- 55 23 -40 -59 -29 -17 Max (60) 2.3 107 (1.0) 65 33 -35 -- -- -- Unit MHz V dB dB dB dB dB dBm dBm dBm Gain 1 - Gain 3 in any 20dB window Vcont = 2.3V Vcont = 1.5V Vcont = 0.15V Gain = 50dB Gain = 10dB Gain = -30dB Test Conditions
Note: ( ) : These data are actual spread, not guaranteed.
HD155101BF
* Specifications of IQ Demodulator
Item Power gain i/p CP o/p CP IQ phase accuracy IQ amplitude mismatch Output DC offset voltage IQ differential output swing I/Q common mode output voltage Min -0.5 (-17.5) (-19.0) -1.0 (-0.5) -60 2.4 1.1 Typ 1.4 -16.0 -15.6 0 0.1 0 3.0 1.3 Max 3.5 (-14.0) (-12.0) 1.0 (0.5) 60 -- 1.5 Unit dB dBm dBm deg. dB mV Vp-p V Test Conditions IF2 = 45MHz, Pin = -25dBm, Rout = 10k, IFLO = 540MHz, Pin = -10dBm IF2 = 45MHz, Baseband = 67.7kHz, IFLO = 540MHz, Pin = -10dBm IF2 = 45MHz, Baseband = 67.7kHz, IFLO = 540MHz, Pin = -10dBm Baseband = 67.7kHz Baseband = 67.7kHz |IOUT - IOUTB| and |QOUT - QOUTB| Baseband = 67.7kHz |IOUT - IOUTB| and |QOUT - QOUTB| VCC = 3.0V
Note: ( ) : These data are actual spread, not guaranteed.
HD155101BF
* Specifications of IQ Modulator and Offset PLL (RFLO and IFLO signals are supplied by Signal Generator)
Item Frequency (RF) Frequency (LO) Frequency (IF) Power up time Lock up time Carrier suppression ratio Upper side-band suppression ratio Phase accuracy (PN9, GMSK) Modulation spurious (PN9, GMSK) Min 880 1055 (120) -- -- 31 35 -- -- -- -- -- -- -- -- Tx noise in RX band (Tx power = 0dBc = 30dBm) Isolation of the 1st local input to TXVCO input IQ differential input swing I/Q common mode input voltage -- -- (40) -- (0.8) Typ 902 1172 135 0.3 20 40 45 0.94 2.27 -36.5 -70.0 -74.0 -77.0 -80.5 -82.0 -157 -165 43 2.0 1.0 Max 915 1260 (180) (0.5) (80) -- -- (2.5) (6.0) (-33.0) (-63.0) (-63.0) (-66.0) (-68.0) (-74.0) (-151) (-163) -- (2.4) (1.2) Unit MHz MHz MHz sec sec dBc dBc deg. rms deg. peak dBc dBc dBc dBc dBc dBc dBc/Hz dBc/Hz dB Vp-p V |IIN - IINB| and |QIN - QINB| from PS mode from PS mode to 915MHz All `1' GMSK (Baseband = 67.7kHz) I/Q differential input swing = 2.0Vp-p I/Q common mode input voltage = 1.0V 200kHz Bandwidth 200kHz Bandwidth 200kHz offset / 30kHz Bandwidth 400kHz offset / 30kHz Bandwidth 600kHz to 1.8MHz offset / 30kHz Bandwidth 1.8MHz to 3MHz offset / 100kHz Bandwidth 3MHz to 6MHz offset / 100kHz Bandwidth 6MHz upwards offset / 100kHz Bandwidth 925MHz to 935MHz (10MHz up from Tx band) 935MHz to 960MHz (20MHz up from Tx band) Test Conditions (Loop bandwidth = 1.4MHz)
Note: ( ) : These data are actual spread, not guaranteed.
J803 (MIX1RF) SMA
J802 (MIX1LO) SMA
VCC
J801 (MIX1IF) J702 (MIX2RF) SMA SMA
Test Circuit
C807 1000p 4 4 65
C805 1000p
R701 0
1000p 100p L802 3.3n L803 C812 10n 3p C701 48 47 46 45 44 43 42 41 40 39 38 37 1000p C702 1000p C703 3300p C610 3300p C609 3300p C608 3300p VCC C606 47p VCC C704 3300p 3p C810 1000p 100n 6p 100n C801 L701 C705 L801 C803 1000p C706 7p
TX
X1
3 3 2 2 11
C813 4p C809 C808
C811 2.5p
T801 617PT-1206
J701 (MIX2IF/AGCIN) SMA
X2
T701 617DB-1018 3 4 3 4 2 2 11 65
L201
IFIN VCCIF GNDIF IFINB MIX2O MIX1IN RFLOIN
AOUT) SMA C201
MIX1INB VCCMIX1 MIX1OUT GNDMIX1 MIX1OUTB POONRX1 POONRX2 RFOUT VCCLNA GNDLNA RFIN POONTX VCCPLL GNDPLL VCOIN VCCCOMP PLLOUT CURAD QINB QIN IINB QOUTB QOUT IOUTB IOUT VCONT AGCOUTB AGCOUT VCCAGC GNDAGC MIX2OB
10n
C202 10p
3p
Q201 BPF420
J601 (AGCOUT) SMA
CC
(LNAIN) SMA C204 IC001
C203 27p
L202
R201
T601 617DB-1018 3 4 3 4 2 2 11 65 C607 3300p
1000p
C207 10n 0.5p
C206 4.7k 0.5p
C205 10p
HD155101BF
GNDDIV
VCCDIV
CC
C301 47p
MP
C302 120p
IIN MODB MOD VCCIQ IFLO GNDIQ IFVCOO IFVCOI
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
C601 1000p C505 C503 6p 6p C506 3p L502 8.2n VARICAP1 R502 HVU355 2.7k C507 8p C508 1000p C907 27p C904 27p C901 27p C502 1000p
IOUTB IOUT QOUT QOUTB VCONT IIN IINB
VCONT IOUT IOUTB QOUT QOUTB
OOUT) SMA R501 100 C504 3p
R307 8.2k
13 14 15 16 17 18 19 20 21 22 23 24
C303 100p
C908 100n C905 100n C902 100n
C909 100000n C906 100000n C903 100000n
VTUNE VCC VCCCOMP VCCVCOEXT
R301 0 C405 8p L401 L402 18n 18n C406 1000p C501 120p L501 15n
R304 18
C304 0.75p
XT
QIN
QINB
POONTX
POONRX2
POONRX1 IIN IINB QIN
VCC GND GND GND
GND
GND
GND
IOUT
QOUTB
VCONT
POONTX
VTUNE
SLEEP
POONRX2
POONRX1
POONRX
HD155101BF
QIN IIN QINB IINB
J501 (IFLO) SMA
VCCVCOEXT
R306 130 C308 3300p
VCC
VCCCOMP
C307 220p
IOUTB
QOUT
QINB
GND
GND
R302 R303 0 0 VCO1 C305 MQE502-902 or 1000p MQE601-902 Kv=11MHz/V 3 4 OUT VCC 2 5 R305 GND GND 220 6 MOD CON 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
VTUNE
HD155101BF
Measurement Results
LNA Measurement Results (for reference only)
Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 3.0 V 1000 p 1 Rbias 100 3 50 Output(RF) 50 1000 p Input(RF) 940 MHz, -50 dBm 10 n 0.5 p 4.7 k 6 0.5 p 10 p 5 7 9 22 30 HD155101BF 35 40 46 3p 10 n 10 p Ic Active bias circuit 2 4 8 11 20 31 34 41 45 Vbias 0.56 V
TRS: Siemens BFP420
Figure 4 Evaluation Circuit for LNA
20 15 Gain [dB], ICP [dBm] 10 5 0 -5 -10 -15 880 Vcc=3.0V Pin=-50dBm Gain [dB] ICP [dBm] NF [dB]
3.5 3 2.5
NF [dB]
2 1.5 1 0.5 0 1020
900
920
940 960 Frequency [MHz]
980
1000
Figure 5 Gain, NF, ICP vs. Frequency
HD155101BF
40 20 0 Pout [dBm] -20 -40 -60 -80 -100 -120 -60 -50 -40 Pout [dBm] IM3 [dBm] Gain [dB] -30 -20 Pin [dBm] -10 0 Interfere(1)=940.8MHz Interfere(2)=941.6MHz Vcc=3.0V Freq.=940MHz 20 19 18 17 16 15 14 13 12 10
Figure 6 Gain, Pout vs. Pin
20 19.5 19 18.5 Gain [dB] 18 17.5 17 16.5 16 15.5 15 2 2.5 3 Vcc [V] 3.5 4 -40 -20 27 80 100 4.5 Freq.=940MHz Pin=-50dBm
Figure 7 Gain vs. Supply Voltage
Gain [dB]
HD155101BF
3 Freq.=940MHz 2.5 2 NF [dB] 1.5 1 0.5 0 2 -40 -20 27 80 100 2.5 3 Vcc [V] 3.5 4 4.5
Figure 8 NF vs. Supply Voltage
-7 -8 -9 -10 ICP [dBm] -11 -12 -13 -14 -15 -16 -17 2 2.5 3 Vcc [V] 3.5 4 -40 -20 27 80 100 4.5 Freq.=940MHz
Figure 9 ICP vs. Supply Voltage
HD155101BF
8 7.5 7 Icc@TRS [mA] 6.5 6 5.5 5 4.5 4 2 -40 -20 27 80 100
2.5
3 Vcc [V]
3.5
4
4.5
Figure 10 LNA Transistor Current vs. Supply Voltage
HD155101BF
1st Mixer Measurement Results
Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V Load: 400 ohm Balanced TOKO: 617PT-1206 800 : 50 Insertion loss: 1.5 dB@225 MHz 3.0 V 1000 p 1 Input (LO) 1165 MHz, -10 dBm 50 2.5 p 1000 p 44 3.3 n 50 4 p 47 10 n 48 3p 5 7 9 22 30 35 40 46 2 4 8 11 20 31 34 41 45 Lo Buff2 43 Lo Buff Gilbert Cell Mix 42 100 n 1000 p Vcc
3p 1000 p Output (IF) 225 MHz 50
Input (RF) 940 MHz, -50 dBm
Figure 11 Evaluation Circuit for 1st Mixer
10
16
5 C.G. [dB], ICP [dBm] C.G. [dB] 0 ICP [dBm] NF SSB [dB] Vcc=3.0V Pin=-50dBm Pin(LO)=-10dBm Freq.IF=225MHz
14
12
-5
10
-10
8
-15 880
900
920
940 960 Frequency [MHz]
980
1000
6 1020
Figure 12 Gain, NF, ICP vs. Frequency
NF SSB [dB]
HD155101BF
10 Pout[dBm] 0 -10 Pout [dBm] -20 -30 -40 -50 -60 Vcc=3.0V Freq.RF=940MHz Freq.LO=1165MHz Pin(LO)=-10dBm Freq.IF=225MHz -50 -40 -30 -20 Pin[dBm] -10 0 C.Gain[dB] 15 20
10 C.Gain [dB] NF SSB [dB]
5
0 -5 -10 10
Figure 13 Input-Output Characteristics
10
25
5 NF SSB[dB] C.Gain[dB]
20
C.Gain [dB]
0
15
-5 Freq.RF=940MHz Freq.LO=1165MHz Freq.IF=225MHz Pin(RF)=-50dBm -50 -40 -30 -20 Plo [dBm] -10
10
-10
5
-15 -60
0
0 10
Figure 14 CG, NF vs. Local Input Power
HD155101BF
12 10 C.Gain[dB] 8 C.Gain [dB] 6 4 2 0 -2 150 Vcc=3.0V Freq.LO=1165MHz Pin(LO)=-10dBm Pin(RF)=-50dBm 200 Frequency [MHz] 250 300
Figure 15 Output Frequency Characteristics
10 9 8 7 C.Gain [dB] 6 5 4 3 2 1 0 2 2.5 3 Vcc [V] 3.5 4 -40 -20 27 80 100 4.5
Figure 16 Gain vs. Supply Voltage
HD155101BF
15 14 13 12 SSB NF [dB] 11 10 9 8 7 6 5 2 2.5 3 Vcc [V] 3.5 4 4.5 -40 -20 27 80 100
Figure 17 NF(SSB) vs. Supply Voltage
-7 -8 -9 -10 ICP [dBm] -11 -12 -13 -14 -15 -16 -17 2 2.5 3 Vcc [V] 3.5 4 -40 -20 27 80 100 4.5
Figure 18 ICP vs. Supply Voltage
HD155101BF
IF AMP + 2nd Mixer Measurement Results
Conditions: 3.0 V Vcc = 3.0 V 1000 p POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 50 7 p 39 100 n 38 6p 21 0.01 5 270 MHz Divider 1/2 7 9 300
1
2
4
8 11 20 31 34 41 45 150 Mixer2 150 37
Output test-circuit for IF AMP + Mixer2 evaluation only 1000 p 1000 p 36 1000 p Output (MIX2) 45 MHz
IF AMP
Input (1st IF) 225 MHz, -40 dBm
1000 p
Input (IFLO) 540 MHz, -10 dBm
50
200 : 50 TOKO 617DB-1018 Insertion loss = 3.6 dB
AGC 22 30 35 40 46
Figure 19 Evaluation Circuit for IF AMP + 2nd Mixer
20 C.Gain Pout_2IF 15 C.Gain [dB] 1dB
0
-10 -20 -30 -40 ICP: -25dBm -50 0 10 Pout_2IF [dBm]
10
5
0
-5 -70
-60
-50
-40
-30 -20 Pin_RF [dBm]
-10
Figure 20 Input-Output Characteristics, 1dB-Compression Point
HD155101BF
20.0 0.0 -20.0 -40.0 -60.0 -80.0 -100.0 -60 IP3in: -16.0dBm -50 -40 -30 Pin_RF [dBm] -20 -10 0 Pout_IM3 Pout_2IF IF11=225.8MHz IF12=226.6MHz IP3out: -4.0dBm
Pout [dBm]
Figure 21 Intermodulation 3rd Characteristics
20 10 0 C.Gain [dB] -10 -20 -30 -40 -50 -50 -40 -30 -20 Local in [dBm] -10 2.5V 27C 2.7V 27C 3.0V 27C 4.0V 27C IF1=225MHz/Pin=-30dBm, IFLO=540MHz,IF2=45MHz
0
10
Figure 22 C.Gain vs. Local in Power
HD155101BF
20 25
10 C.Gain [dB]
C.Gain Ta=-30C Ta=25C Ta=80C 2.7V to 3.6V
20 NF SSB [dB]
0 -10 -20 -30 2
15
10
5 NF SSB 0 4.5
2.5
3 Vcc [V]
3.5
4
Figure 23 C.Gain, NF SSB vs. Supply Voltage
ICP(Input Compresion Point) [dBm]
-20 Vcc=4.0V Vcc=3.0V Vcc=2.7V
-25
IF1=225MHz, IFLO=540MHz/Pin=-10dBm, IF2=45MHz -30 -40 -20 0 20 40 Temperature [deg] 60 80 100
Figure 24 ICP vs. Temperature
HD155101BF
AGC Measurement Results
3.0 V 1000 p 1 45 MHz 50 1000 p 37
POONRX1
2
4 150
8 150
11 20 31 34 41 45 Mixer2 output R 2k 33
Output test-circuit for AGC block evaluation only Output (MIX2) 200 : 50 45 MHz 3300 p 32 3300 p 3300 p
1000 p 50 : 200
POONRX2
36
ATT AGC AMP 300
TOKO 617DB-1018 insertion loss = 3.6 dB
Power on/off control
Linearizer
IQ Demodulator IF AMP + Mixer2 IF VCO Divider LNA & Mixer 1 Transmitter block
29 2k
TOKO Vcont 617DB-1018 0.15 to 2.3 V insertion loss = 6.1 dB Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V
IQ Demo 40 46
5
7
9
22
30
35
Figure 25 Evaluation Circuit for the AGC & Power On Control Blocks
80 60 40 Gp [dB] 20 0 -20 -40 -60 0 Ta=-40C Ta= 27C Ta= 90C
Vcc=3.0V, Freq=45MHz, Zin=300 0.5 1 Vcont [V] 1.5 2 2.5
Figure 26 Power Gain vs. Vcont Voltage
HD155101BF
60 55 50 Gp [dB] 45 40 35 30 10 Ta=-40C Ta= 27C Ta= 90C
Vcc=3.0V, Vcont=2.3V, Freq=45MHz, Pin=-100dBm, Zin=300 20 Frequency [MHz] 50 100
Figure 27 Power Gain vs. Frequency
60 50 40 NF [dB] 30 20 10 0 -40 VCC=3V, freq.=45MHz Ta=-40C Ta=27C Ta=90C
-20
0
20 Gp [dB]
40
60
80
Figure 28 Noise Figure(NF) vs. Power Gain(Gp)
HD155101BF
10 0 -10 ICP [dBm] -20 -30 -40 -50 -60 -70 -40 -20 0 Gp [dB] 20 40 60 Vcc=3V, freq.=45MHz Ta=-40C Ta=27C Ta=90C
Figure 29 Input Compression Point(ICP) vs. Power Gain(Gp)
60 40 20 Gp [dB] 0 -20 -40 -60 -80 1.5 Ta=-40@Vcont=2.3 Ta=27@Vcont=2.3 Ta=90@Vcont=2.3 Ta=-40@Vcont=0.15 Ta=27@Vcont=0.15 Ta=90@Vcont=0.15 Freq=45MHz, Zin=300
2
2.5
3 Vcc [V]
3.5
4
4.5
Figure 30 Power Gain(Gp) vs. Supply Voltage(Vcc)
HD155101BF
IQ Demodulator Measurement Results
Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 3.0 V POONRX2 (pin 2) = 3.0 V POONTX (pin 7) = 0 V 1 TOKO 45 MHz 617DB-1018 50 3300 p 50 : 200 2 4 8 11 20 31 34 41 45 10 k AGC 2k 33 32 90 MHz divider 21 0.01 5 /6 2k 2nd order Butterworth filter 45 MHz 2nd order Butterworth filter 10 k 28 27 26 IOUT IOUTB QOUT V 25 QOUTB V 10 k 10 k 10 k 10 k
3.0 V 1000 p
3300 p Input (IFLO) 540 MHz, -10 dBm
3300 p 50
/2 (90 phase shifter) 7 9 22 30 35 40 46
Single ended 1k input impedance Single ended 10k load impedance
Figure 31 Evaluation Circuit for the I&Q Demodulator Block
HD155101BF
-10 Output [dBm] (Single ended) -15 -20 -25 -30 -35 -35
Gp[dB] Vcc=3.0V Gp[dB] Vcc=2.7V Gp[dB] Vcc=3.6V Output[dBm] Vcc=3.0V Output[dBm] Vcc=2.7V Output[dBm] Vcc=3.6V
30
20 Ta = 25C 1dB 0 -10 -20 0 10
OCP: -15.0dBm
ICP: -15.5dBm -30 -25 -20 -15 -10 Input [dBm] (Single ended) -5
Figure 32 Input-Output Characteristics
-10 Output [dBm] (Single ended) -15 -20 Vcc = 3V -25 -30 -35 -35
Gp[dB] Ta=25C Gp[dB] Ta=-20C Gp[dB] Ta=80C Output[dBm] Ta=25C Output[dBm] Ta=-20C Output[dBm] Ta=80C
30 20 10
0 -10 -20 0
-30
-25 -20 -15 -10 Input [dBm] (Single ended)
-5
Figure 33 Input-Output Characteristics
Gp [dB]
Gp [dB]
HD155101BF
GMSK modulated signal (All 1 GMSK) DIV f1: 45.8MHz (45MHz) + (67.7kHz) DEM f2: 46.6MHz 0 Output [dBm] (Single ended) -10 -20 -30 -40 -50 -35 Output [dBm] IM3 [dBm] -30 OIP3: -0.2dBm
IIP3: -2.7dBm 0
-25 -20 -15 -10 -5 Input [dBm] (Single ended)
Figure 34 Inter Modulation 3rd Characteristics
Rejection @200k @400k @600k @800k @1600k @3000k @20000k 20 0 -20 -40 -60 -80 10 fc: 210kHz spec.1 spec.2 Iout Qout spec.(Min) -0.3dB -4.0dB -9.4dB -14.0dB -25.9dB -36.8dB -50.0dB Iout -2.6dB -11.5dB -21.3dB -29.0dB -43.3dB -42.2dB -54.7dB Qout -2.4dB -11.2dB -21.1dB -28.7dB -43.0dB -42.0dB -56.1dB
Rejection level [dB]
100
1000
104
105
HD155101BF
0.09[degree]
0.1[dB]
a) I&Q Phase Accuracy
b) I&Q Amplitude Mismatch
1.38[V]
3.00[Vp-p]
c) Common Mode Voltage
d) Differential Output Swing
Figure 36 Demodulator Output Waveforms (67.7 kHz) at Vcc = 3.0 V, Ta = 25C
HD155101BF
Transmitter Measurement Results
3.0 V 1000 p 1 Input(LO),-10dBm 50 1150 to 1185MHz Spectrum analyzer 50 1000p GMSK RF TX. signal 890 to 915MHz MURATA MQE502-902 or MQE601-902 Kv=11MHz/V,C3=100pF loop band width=1.5MHz 18 VCO 5.0V R3 220 C2 3300p R2 130 3p 51 p
RFLOIN
2
4
8
20
31
34
41
45
14 LO buffer
1st. local signal 1150 to 1185 MHz I&Q modulator block Down-converter (offset mixer) VCO buffer Low pass filter /2 (90 phase shifter) 270 MHz Q baseband signal 100 kHz I baseband signal 100 kHz
3.9n
VCOIN
10
0.75 p
VCCCOMP
11 I3 12 I1
1000p
PLLOUT on
GMSK modulated IF 270 MHz
C1 220p
ICURAD
off
I2 Phase detector
13
RICURAD 8.2k
Low SW1 Charge Pump pass (Current mode driver) filter Power save control POONTX=H, SW1=Off MODB MOD 5 7 9 22 30 35 40 46 18 19 14 QINB 15 QIN 16 IINB
17 IIN
21 IFLO 0.01 50 Input(IFLO) 540MHz, -10dBm
Conditions: Vcc = 3.0 V POONRX1 (pin 1) = 0 V POONRX2 (pin 2) = 0 V POONTX (pin 7) = 3.0 V
18n Vcc
8p 18n
fo=270MHz I&Q baseband signal generator
Figure 37 Evaluation Circuit for the Upconverter (I&Q Modulator and Offset PLL Block)
5
I1 peak, I2 peak, I3 [mA]
4
I1 peak I2 peak I3
3
2
1
0 2
4
6 R
8
10 [k]
20
30
HD155101BF
Phase accuracy and lock up time characteristics depend on the OPLL loop bandwidth. The following table shows measurement result of each characteristic, when the OPLL loop bandwidth is changed. Table 2 Measurement Results of Transmitter Characteristics vs. OPLL Loop Bandwidth Dependence (RICURAD = 8.2 k, IFLO generated by signal generator)
Conditions Item VCO & Phase detector
Condition1 Condition 2 Condition 3 Condition 4 Condition 5
Unit
VCO: MURATA MQE502-902 or MQE601-902, C3 = 100 pF in VCO, RICURAD = 8.2 k, kvr = 2 x 11 x 106 (rad/Vsec), k dr = ( 2.83 x 10-3) / (A/rad) 0.8 680 10.0 100 68 390 1.1 390 6.8 100 100 330 1.3 300 4.7 100 110 270 1.5 220 3.3 100 130 220 1.6 180 2.7 100 130 200 MHz pF nF pF
Loop bandwidth (measured) C1 C2 C3 R2 R3
Item 200 kHz offset 400 kHz offset 600 kHz to 1.8 MHz offset 1.8 MHz to 3 MHz offset 3 MHz to 6 MHz offset 6 MHz upwards offset Carrier suppression Side band suppression Phase accuracy PN9 PN9 All `1' All `1' Lock up time Tx noise in Rx band VCO noise only
Spec. -33 -63 -63 -66 -68 -74 31 35 2.5 6.0 2.5 6.0 80 925 MHz 935 MHz 925 MHz 935 MHz
Measured1
Measured2
Measured3
Measured4
Measured5
Unit dBc dBc dBc dBc dBc dBc dBc dBc deg. rms deg. peak deg. rms deg. peak sec dBc/Hz dBc/Hz dBc/Hz dBc/Hz
-37.23 -67.41 -72.86 -79.65 -82.11 -82.77 47.35 39.10 1.53 3.30 0.99 2.26 58.1 -163.3 -166.4
-37.09 -67.95 -72.85 -76.96 -81.11 -82.67 48.44 39.47 1.16 2.90 0.95 2.33 41.1 -158.6 -165.6
-37.60 -68.49 -73.09 -76.45 -80.83 -82.59 47.54 39.89 1.02 2.81 0.93 2.33 29.4 -157.0 -165.4
-37.70 -68.94 -73.48 -75.70 -79.18 -81.98 46.71 39.89 0.89 2.72 0.93 2.31 19.1 -155.1 -164.1
-37.86 -69.23 -73.26 -74.96 -79.58 -82.38 48.36 40.33 0.84 2.64 0.89 2.04 17.2 -154.9 -163.3
-165.2 (0 dBc = -0.5 dBm, noise -165.7 dBm/Hz) -166.4 (0 dBc = -0.5 dBm, noise -166.9 dBm/Hz)
HD155101BF
3.0 Mod: PN9 Phase accuracy [deg. rms] 2.5 2.0 1.5 1.0 0.5 0 0.6
0.8
1.0 1.2 1.4 OPLL Loop Bandwidth [MHz]
1.6
1.8
Figure 39 Phase Accuracy vs. OPLL Loop Bandwidth
60 50 PS mode to 915MHz Lock Up Time [sec] 40 30 20 10 0 0.6
0.8
1.0 1.2 1.4 OPLL Loop Bandwidth [MHz]
1.6
1.8
Figure 40 Lock Up Time vs. OPLL Loop Bandwidth
HD155101BF
-150 Tx Noise in Rx Band [dBc/Hz]
-155 925MHz -160
-165
935MHz
-170 0.6
0.8
1.0 1.2 1.4 OPLL Loop Bandwidth [MHz]
1.6
1.8
Figure 41 Tx Noise in Rx Band vs. OPLL Loop Bandwidth
HD155101BF
Transmitter Measurement Results (1) (RICURAD = 8.2 k and IFLO generated by signal generator)
VCC 50 Input(LO) -10dBm 1160 to 1185MHz 2.5p 1000p 3.3n 0.01 00 0.01
IFIN
IFINB
MIX1OUTB
MIX1OUT
MIX1IN
MIX1INB
RFLOIN
GNDMIX1
VCCMIX1
MIX2O
GNDIF
VCCIF
48 47 46 45 44 43 42 41 40 39 38 37
VCC 3V VCCCOMP 5V
+
33
0.01
+
33
0.01
1 2 3 4 5 6 7 8 9 10 11 12
POONRX1 POONRX2 RFOUT VCCLNA GNDLNA RFIN POONTX VCCPLL GNDPLL VCOIN VCCCOMP PLLOUT CURAD
MIX2OB GNDAGC VCCAGC AGCOUT AGCOUTB VCCDIV GNDDIV VCONT IOUT IOUTB QOUT QOUTB IFVCOO IFVCOI GNDIQ VCCIQ
HD155101BF
36 35 34 33 32 31 30 29 28 27 26 25
VCC 0.01 0 0 0.01
MODB
QINB
MOD
RICURAD 8.2k Spectrum Analyzer 50 100p 18 0.75p I&Q baseband Signal Generator 8p VCO VCCVCO 4.7V 220 130 3300p 220p VCC 0.01 18n 18n 0.01 50 Input(IFLO) -10dBm 540MHz
+
33
0.01 MURATA MQE502-902
Figure 42 Evaluation Circuit Using Signal Generator for the I&Q Modulator and Offset PLL Table 3
Item Measured frequency 200 kHz offset 400 kHz offset 600 kHz to 1.8 MHz offset 1.8 MHz to 3 MHz offset 3 MHz to 6 MHz offset 6 MHz upwards offset Carrier suppression Side band suppression Phase accuracy PN9 PN9 All `1' -33 -63 -63 -66 -68 -74 31 35 2.5 6.0 2.5
Measurement Results Using SG (RICURAD = 8.2 k, IFLO generated by signal generator)
Spec. Measured1 890 -36.36 -68.22 -74.84 -77.48 -79.73 -81.63 46.24 38.81 1.05 2.76 1.00 Measured2 902 -36.16 -67.30 -74.88 -77.30 -79.47 -80.67 46.11 38.86 1.05 2.61 1.02 Measured3 915 -36.60 -67.02 -74.69 -77.10 -79.16 -80.94 45.98 38.84 1.05 2.59 1.01 Unit MHz dBc dBc dBc dBc dBc dBc dBc dBc deg. rms deg. peak deg. rms
13 14 15 16 17 18 19 20 21 22 23 24
IFLO
IINB
QIN
IIN
HD155101BF
a-1. Spectrum1 (890MHz, PN9)
a-2. Spectrum2 (890MHz, PN9)
b-1. Spectrum1 (902MHz, PN9)
b-2. Spectrum2 (902MHz, PN9)
c-1. Spectrum1 (915MHz, PN9)
c-2. Spectrum2 (915MHz, PN9)
Figure 43 GMSK Modulated Transmitter Output Spectrum (890 MHz, 902 MHz, 915 MHz)
HD155101BF
T=-40C
902MHz, PN9
T=-40C
902MHz, PN9
T=27C
902MHz, PN9
T=27C
902MHz, PN9
T=100C
902MHz, PN9
T=100C
902MHz, PN9
Figure 44 GMSK Modulated Transmitter Output Spectrum vs. Temperature
HD155101BF
The Acquisition response of OPLL using 8.2 k icurad is shown below. The control voltage of the VCO was observed by the digital storage oscilloscope.
0.5V/div
0.5V/div
12.8s 5s/div
19.95s 5s/div
a. from PS mode to 902MHz lock
b. from PS mode to 915MHz lock
Figure 45 Acquisition Time (Lock Up Time)
HD155101BF
Transmitter Measurement Results (2) (RICURAD = 8.2 k and IFLO using an internal IFVCO)
VCC 50 Input(LO) -10dBm 1160 to 1185MHz 1.5p 18p 00 4.7n 0.01
IFIN
IFINB
MIX1OUTB
MIX1OUT
MIX1IN
MIX1INB
RFLOIN
GNDMIX1
VCCMIX1
MIX2O
GNDIF
VCCIF
48 47 46 45 44 43 42 41 40 39 38 37
VCC 3V VCCCOMP 5V
+
33
0.01
+
33
0.01
1 2 3 4 5 6 7 8 9 10 11 12
POONRX1 POONRX2 RFOUT VCCLNA GNDLNA RFIN POONTX VCCPLL GNDPLL VCOIN VCCCOMP PLLOUT CURAD
MIX2OB GNDAGC VCCAGC AGCOUT AGCOUTB VCCDIV GNDDIV VCONT IOUT IOUTB QOUT QOUTB IFVCOO IFVCOI GNDIQ VCCIQ
HD155101BF
36 35 34 33 32 31 30 29 28 27 26 25
VCC 0.01 0 0 0.01
MODB
QINB
MOD
IFLO
IINB
QIN
IIN
Vtune 27p 8.2n 10p 18k 4700p 6p 12k HVU355 330p 0 0
8.2k Spectrum Analyzer 50 100p 18 0.75p I&Q baseband Signal Generator VCO VCCVCO 4.7V 220 130 3300p VCC 0.01 220p 11p 18n 0.01 8.2n 18n 0.01 10 10 100
13 14 15 16 17 18 19 20 21 22 23 24 10p 27 27p
0.1
100p
+
33
0.01 MURATA MQE502-902
VCCPLL 3V
+ 33
Figure 46 Evaluation Circuit Using Internal IFVCO for the I&Q Modulator and Offset PLL Table 4
Item Measured frequency 200 kHz offset 400 kHz offset 600 kHz to 1.8 MHz offset 1.8 MHz to 3 MHz offset 3 MHz to 6 MHz offset 6 MHz upwards offset Carrier suppression Side band suppression Phase accuracy PN9 PN9 All `1' -33 (-30) -63 (-60) -63 (-60) -66 (-63) -68 (-65) -74 (-71) 31 35 2.5 (5) 6.0 (20) 2.5
Measurement Results Using an Internal IFVCO (RICURAD = 8.2 k)
Spec. (GSM Spec.) Measured1 890 -35.64 -63.63 -69.85 -76.89 -81.06 -82.67 41.87 43.59 2.43 6.56 0.95 Measured2 902 -36.24 -64.09 -69.95 -76.50 -80.67 -82.40 42.50 44.35 2.09 6.06 0.93 Measured3 915 -36.93 -64.09 -70.47 -76.04 -80.38 -82.34 42.42 43.25 2.01 6.41 0.96 Unit MHz dBc dBc dBc dBc dBc dBc dBc dBc deg. rms deg. peak deg. rms
1 2 3 4 5 6 7 8 9 10 0.1
20 19 18 17 16 15 14 13 12 11 LMX2336 (PLL syn)
HD155101BF
a-1. Spectrum1 (890MHz, PN9)
a-2. Spectrum2 (890MHz, PN9)
b-1. Spectrum1 (902MHz, PN9)
b-2. Spectrum2 (902MHz, PN9)
c-1. Spectrum1 (915MHz, PN9)
c-2. Spectrum2 (915MHz, PN9)
Figure 47 GMSK Modulated Transmitter Output Spectrum Using an Iternal IFVCO
HD155101BF
570 Vcc=3.0V 560 Frequency [MHz]
550
540
530
520 0
0.5
1
1.5 Vtune [V]
2
2.5
3
Figure 48 IFVCO Oscillation Frequency vs. Vtune Voltage
0.2V/div
278s
100s/div
Figure 49 IFVCO Lock Up Time (from PS mode to 540 MHz)
HD155101BF
Package Dimesions
Unit: mm 9.0 0.2 7.0 36 25 9.0 0.2 37 24 0.5
M
48 12
13
0.17 0.05 0.15 0.04
1.70 Max
1 0.21 0.05 0.19 0.04 0.75
0.08
1.00 0.75 0 - 8 0.50 0.10
0.10
0.10 0.07
1.40
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-48 Conforms 0.2 g
HD155101BF
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447

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